1. Field of the Invention
The present invention relates to a compound semiconductor device which is characteristically noiseless, and a manufacturing method thereof. More particularly, it relates to a compound semiconductor device in which a void is formed on the substrate so that backside current does not occur and transconductance is high.
2. Description of the Related Art
Recently, rapid advances toward superspeed computers, extremely high frequency and optical communications have increased. But a conventional silicon (Si) device cannot sufficiently satisfy these needs. At present, a study of compound semiconductors having excellent material characteristics is being actively pursued.
GaAs compound semiconductors are suitable for military and space communication use because they operate faster than Si. They have lower power consumption due to better electronic characteristics, such as high electron mobility and semi-insulating properties. Accordingly, many kinds of devices utilize the excellent material characteristics of GaAs. These devices include metal semiconductor field effect transistors (hereinafter, termed as "MESFET"), heterojunction bipolar transistors and high electron mobility transistors.
The MESFET is a basic GaAs device in which source and drain electrodes form ohmic contacts with a cap layer and are in Schottky contact with each other so that current flow is controlled by a voltage applied to a gate electrode in the MESFET. Meanwhile, a delta doped MESFET (hereinafter, referred as .delta.-MESFET) refers to a transistor which has a low-noise characteristic and a high operation speed due to two-dimensional electron gas (hereinafter, termed as "2DEG") that is generated by forming multiple atomic layers (such as Si) on the MESFET.
FIG. 1 shows the conventional .delta.-MESFET structure. An undoped I-type GaAs buffer layer 12, a channel 13 delta-doped by multiple atomic layers, such as Si, and an I-type GaAs spacer layer 14 are sequentially formed on the surface of a semi-insulating GaAs semiconductor substrate 11. N.sup.+ type well regions 15, which overlap the buffer layer 12, are formed at both sides of the spacer layer 14. Source and drain electrodes 17 and 18 are formed on the well regions 15 by an ohmic contact. A gate electrode 16 is formed by a Schottky contact on a portion of the surface of the spacer layer 14 (excluding the well regions 15).
A manufacturing method of the above-described .delta.-MESFET is as follows. First, the I-type GaAs buffer layer 12, the channel 13 comprising multiple atomic layers of Si, and the I-type GaAs spacer layer 14 are sequentially formed on the surface of the semi-insulating GaAs semiconductor substrate 11 by molecular beam epitaxy (hereinafter, termed as "MBE") or metal organic chemical vapor deposition (hereinafter, termed as "MOCVD"). The gate electrode 16 is formed on the surface of the spacer layer 14. The N.sup.+ -type well regions 15 are formed by implanting N-type impurities (such as Si) into both sides of the gate electrode using an ion implantation mask and heat-treatment. The source and drain electrodes 17 and 18 are subsequently formed on the well regions 15 by a lift-off process.
Current flow through the channel 13 is controlled by the intensity of the reverse voltage applied to the gate 16 in the .delta.-MESFET. Leakage current through the semiconductor substrate 11 is prevented because the buffer layer 12 increases the resistance by lowering the concentration of the impurities down to about 10E14 ions/cm.sup.3. Moreover, the buffer layer 12 provides a depletion region between the channel 13 and the semiconductor substrate 11 by generating a voltage difference between electrodes of neighboring elements and a substrate in integrated circuits. The buffer layer also narrows the width of a current path to prevent backgating effects which cause increase of threshold voltage and source resistance.
However, because multiple layers are to be formed in one chamber, impurities doped into other layers increase the concentration of impurities in the buffer layer and lower the resistance, resulting in leakage current and backgating effects. Moreover, this concentration increase makes it difficult to grow crystals because the impurity concentration of the buffer layer should be low. Besides, the length of the gate electrode of each device is shortened to achieve high integration, resulting in a short channel effect and decreasing the threshold voltage. An additional mask is required during ion implantation to decrease the ohmic contact resistance of the source and drain electrodes, further complicating the manufacturing process.